1. Field of the Invention
The present invention relates to phase-locked loop (PLL) circuits.
2. Description of the Related Art
PLL circuits are widely used in many applications. Application examples include clock and data recovery, clock synthesis, frequency synthesis, modulator and de-modulator. Generally, a PLL circuit is employed to provide an output clock which follows an input clock closely.
A conventional PLL circuit 100 as shown in FIG. 1 includes a phase frequency detector (PFD) 103, a charge pump 105, a loop filter 107, a voltage controlled oscillator (VCO) 109 and a frequency divider 111. The frequency divider 111 generates a feedback clock 102 by dividing an output clock FVCO by a divider factor N. The PFD 103 detects a phase difference between a reference clock Fref 101 and the feedback clock 102. Depending on whether the reference clock Fref 101 leads or lags the feedback clock 102, the charge pump 105 generates a charge pump current Icp to deliver either positive or negative charge pulses to the loop filter 107. These charge pulses are integrated by the loop filter 107 to generate an oscillator control voltage Vctrl. The oscillator control voltage Vctrl moves the output clock FVCO of the VCO 109 up or down until the phases of the reference clock Fref 101 and the feedback clock 102 are synchronized. The loop filter 107 may further include a loop resistor 113 and a loop capacitor 115 coupled in series. The divider factor N is determined by a desired frequency of the output clock FVCO With a constant divider factor N, the PLL circuit 100 can force the output clock FVCO to be exactly N times the reference clock Fref 101.
A damping factor δ and a natural frequency ωn of the PLL circuit 100 are given by the following equations:
                    δ        =                                            R              p                        2                    ⁢                                                                      I                  cp                                ⁢                                  K                  VCO                                ⁢                                  C                  p                                                            2                ⁢                π                ⁢                                                                  ⁢                N                                                                        (        1        )                                          ω          n                =                                                            I                cp                            ⁢                              K                VCO                                                    2              ⁢              π              ⁢                                                          ⁢                              C                p                            ⁢              N                                                          (        2        )            where KVCO is a tuning sensitivity of the VCO 109 in radian/volt, Icp is the charge pump current, N is the divider factor, Rp is the resistance of the filter resistor 113 and Cp is the capacitance of the filter capacitor 115.
The natural frequency ωn indicates response quality of the PLL circuit 100. The damping factor δ can be used to examine transient quality of the PLL circuit 100. If an improper damping factor δ is used, circuit vibrations don't damp out and the PLL circuit 100 becomes unstable. Generally, smaller damping factors give better rejection but larger transients. Larger damping factors have better behaved frequency response but they are sluggish in acquisition time response. The optimum damping factor δ is 0.707 which is often designed as the target value of a good compromise between acquisition time response and frequency response.
Referring to the equations (1) and (2), it can be observed that the damping factor δ and the natural frequency ωn of the PLL 100 are dependent on physical elements, such as resistors, capacitors, currents, etc., which have significant variations over manufacturing process and operation environments. Moreover, in order to save the use of discrete components, the filter resistor 113 and the filter capacitor 115 may be implemented on-chip. However, during the integrated circuit fabrication, all of these PLL parameters will vary in a certain range and performance of the PLL circuit 100 will be impacted if variations in these PLL parameters exceed specified limits and tolerances. For example, on-chip resistance and capacitance variations over the worst case process corners may be as large as ±25%. Hence, the damping factor δ and the natural frequency ωn cannot be kept constant as the designed value irrespectively of manufacturing process and operation environments. Similarly, other critical PLL specifications, such as loop bandwidth, phase noise, switching transient and loop stability, will also deviate from the designed values. For example, the damping factor δ is intrinsically related to the stability and phase margin of the PLL circuit. Also, the loop bandwidth is a function of the damping factor δ. Many applications require a constant loop bandwidth over the entire output frequency range, and the optimum loop bandwidth should be larger than the largest baseband spectral frequency.